Structure and method to prevent epi short between trenches in finfet edram

ABSTRACT

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

BACKGROUND

The present application relates to semiconductor device fabrication, andmore particularly to semiconductor structures and methods that preventelectrical shorts between adjacent deep trenches containing embeddeddynamic random access memory (eDRAM) devices.

Deep trench capacitors are used in a variety of semiconductor chips forhigh areal capacitance and low device leakage. A deep trench capacitormay be employed as a charge storage unit in a dynamic random accessmemory (DRAM), which may be provided as a stand-alone semiconductorchip, or may be embedded in a system-on-chip (SoC) semiconductor chip. Adeep trench capacitor may also be employed in a variety of circuitapplications such as a charge pump or a capacitive analog component in aradio-frequency (RF) circuit.

A deep trench capacitor is typically electrically connected toassociated transistors through a conductive strap structure. Since theconductive strap is normally composed of a conductive semiconductormaterial such as doped polysilicon, and during later selective epitaxyprocesses in the formation of source/drain regions, the epitaxial growthof a semiconductor material may occur on the surface of the conductivestrap structure. As dimensions of semiconductor devices scale, thedistance between neighboring deep trenches becomes smaller. Theepitaxial grown semiconductor material on the conductive strap structuremay extend out of the deep trench to bridge the neighboring deeptrenches, causing shorts between the neighboring deep trench capacitors.As such, structures and methods are needed to prevent epitaxial shortsbetween adjacent deep trenches having eDRAM devices.

SUMMARY

The present application provides methods and structures that alloweffective prevention of electrical shorts between neighboring deeptrenches caused by an epitaxial overgrowth of a semiconductor materialon a conductive strap structure employed to connect a deep trenchcapacitor embedded within the deep trench and associated transistorsduring the formation of source/drain regions in fin field effecttransistors (FinFETs). After forming a laterally contacting pair of asemiconductor fin and a conductive strap structure having a base portionvertically contacting a deep trench capacitor embedded in a substrateand a fin portion laterally contacting the semiconductor fin, conductingspikes that are formed on the sidewalls of the deep trench are removedor pushed deeper into the deep trench. Subsequently, a dielectric capthat inhibits epitaxial growth of a semiconductor material thereon isformed over at least a portion of the base portion of the conductivestrap structure. The dielectric cap can be formed either over anentirety of the base portion having a stepped structure or on a distalportion of the base portion.

In one aspect of the present application, a semiconductor structure isprovided. The semiconductor structure includes a semiconductor finlocated on a substrate, a deep trench capacitor located in a lowerportion of a deep trench in the substrate, and a conductive strapstructure located over the deep trench capacitor. The conductive strapstructure comprises a stepped base portion vertically contacting thedeep trench capacitor and a fin portion extending from the base portionand laterally contacting the semiconductor fin. The stepped base portionhas a first recessed surface located below a topmost surface of thesubstrate by a first depth and a second recessed surface located belowthe topmost surface of the substrate by a second depth that is greaterthan the first depth. The semiconductor structure further includes adielectric cap located over the base portion of the conductive strapstructure and completely filling the deep trench.

In another aspect of the present application, a method of forming asemiconductor structure is provided. The method includes forming a deeptrench extending through a top semiconductor layer, a buried insulatorlayer and into a handle substrate of a semiconductor-on-insulator (SOI)substrate. A deep trench capacitor is then formed in a lower portion ofthe deep trench. After forming a conductive material cap over the deeptrench capacitor to completely fill the deep trench, a laterallycontacting pair of a semiconductor fin and a conductive strap structureis formed by patterning the top semiconductor layer and the conductivematerial cap and removing unwanted portions of remaining portions of thetop semiconductor layer and the conductive material cap. The conductivestrap structure includes a stepped base portion vertically contactingthe deep trench capacitor and a fin portion extending from the baseportion and laterally contacting the semiconductor fin. Next, adielectric cap is formed over the stepped base portion of the conductivestrap structure to fill the deep trench.

In another aspect of the present application, a semiconductor structureis provided. The semiconductor structure includes a fin stack thatincludes a dielectric fin and a semiconductor fin atop the dielectricfin located on a substrate, a deep trench capacitor located in a lowerportion of a deep trench in the substrate, and a conductive strapstructure located over the deep trench capacitor. The conductive strapstructure includes a base portion vertically contacting the deep trenchcapacitor and a fin portion extending from the base portion andlaterally contacting the fin stack. The base portion has a proximalportion over which the fin portion extends and a distal portion that isaway from the fin stack. The semiconductor structure further includes adielectric cap located over the distal portion of the base portion andcompletely filling the deep trench.

In yet another aspect of the present application, a method of forming asemiconductor structure is provided. The method includes forming a deeptrench extending through a top semiconductor layer, a buried insulatorlayer and into a handle substrate of a semiconductor-on-insulator (SOI)substrate. A deep trench capacitor is then formed in a lower portion ofthe deep trench. After forming a conductive material cap over the deeptrench capacitor to completely fill the deep trench, a laterallycontacting pair of a semiconductor fin and a conductive strap structureis formed by patterning the top semiconductor layer and the conductivematerial cap and removing unwanted portions of remaining portions of thetop semiconductor layer and the conductive material cap. The conductivestrap structure includes a base portion vertically contacting the deeptrench capacitor and a fin portion extending from a proximal portion ofthe base portion and adjoined to the semiconductor fin. Next, adielectric cap layer is formed over the laterally contacting pair of thesemiconductor fin and the conductive strap structure and the buriedinsulator layer. The dielectric cap layer and the buried insulator layerare recessed to provide a dielectric cap over a distal portion of thebase portion of the conductive strap structure adjoined to the proximalportion.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a top-down view of a first exemplary semiconductor structureafter forming deep trenches within a semiconductor-on-insulator (SOI)substrate according to a first embodiment of the present application.

FIG. 1B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 1A along the vertical plane B-B′.

FIG. 1C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 1A along the vertical plane C-C′.

FIG. 2A is a top-down view of the first exemplary semiconductorstructure of FIGS. 1A-IC after forming deep trench capacitors.

FIG. 2B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 2A along the vertical plane B-B′.

FIG. 2C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 2A along the vertical plane C-C′.

FIG. 3A is a top-down view of the first exemplary semiconductorstructure of FIGS. 2A-2C after forming conductive material portions overthe deep trench capacitors.

FIG. 3B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 3A along the vertical plane B-B′.

FIG. 3C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 3A along the vertical plane C-C′.

FIG. 4A is a top-down view of the first exemplary semiconductorstructure of FIGS. 3A-3C after forming fin-defining mask structures ontop surfaces of the top semiconductor layer and the conductive materialcaps.

FIG. 4B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 4A along the vertical plane B-B′.

FIG. 4C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 4A along the vertical plane C-C′.

FIG. 5A is a top-down view of the first exemplary semiconductorstructure of FIGS. 4A-4C after forming semiconductor layer portions andconductive material cap portions by patterning the top semiconductorlayer and the conductive material caps.

FIG. 5B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 5A along the vertical plane B-B′.

FIG. 5C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 5A along the vertical plane C-C′.

FIG. 6A is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 5A along the vertical plane C-C′ illustrating theconductive cap portion having a base portion with a planar surface.

FIG. 7A is a top-down view of the first exemplary semiconductorstructure of FIGS. 5A-5C after forming a cut mask comprising aphotoresist layer having a pattern of openings over the fin-definingmask structures, the conductive material cap portions and the buriedinsulator layer.

FIG. 7B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 7A along the vertical plane B-B′.

FIG. 7C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 7A along the vertical plane C-C′.

FIG. 8A is a top-down view of the first exemplary semiconductorstructure of FIGS. 7A-7C after transferring the pattern of openings inthe photoresist layer into a silicon-containing antireflective coating(SiARC) layer and an organic planarization layer (OPL) in the cut mask.

FIG. 8B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 8A along the vertical plane B-B′.

FIG. 8C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 8A along the vertical plane C-C′.

FIG. 9A is a top-down view of the first exemplary semiconductorstructure of FIGS. 8A-8C after removing portions of the fin-definingmask structures and the underlying unwanted portions of thesemiconductor layer portions and portions of the conductive material capportions adjoined the unwanted portions of the semiconductor layerportions.

FIG. 9B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 9A along the vertical plane B-B′.

FIG. 9C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 9A along the vertical plane C-C′.

FIG. 10A is a top-down view of the first exemplary semiconductorstructure of FIGS. 9A-9C after removing conductive material spikes inthe conductive material cap portions from the sidewalls of the deeptrenches to provide conductive strap structures and cavities above theconductive strap structures in the deep trenches.

FIG. 10B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 10A along the vertical plane B-B′.

FIG. 10C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 10A along the vertical plane C-C′.

FIG. 11A is a top-down view of the first exemplary semiconductorstructure of FIGS. 10A-10C after depositing a dielectric cap layer overthe conductive strap structures, the fin-defining mask structures andthe buried insulator layer.

FIG. 11B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 11A along the vertical plane B-B′.

FIG. 11C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 11A along the vertical plane C-C′.

FIG. 12A is a top-down view of the first exemplary semiconductorstructure of FIGS. 11A-11C after forming dielectric caps in thecavities.

FIG. 12B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 12A along the vertical plane B-B′.

FIG. 12C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 12A along the vertical plane C-C′.

FIG. 13A is a top-down view of the first exemplary semiconductorstructure of FIGS. 12A-12C after forming at least one gate structureover a portion of each semiconductor fin.

FIG. 13B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 13A along the vertical plane B-B′.

FIG. 13C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 13A along the vertical plane C-C′.

FIG. 14A is a top-down view of the first exemplary semiconductorstructure of FIGS. 13A-13C after forming source/drain regions onportions of the semiconductor fins on opposite sides of the gatestructures and outer conductive strap structures over the conductivestrap structures.

FIG. 14B is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 14A along the vertical plane B-B′.

FIG. 14C is a cross-sectional view of the first exemplary semiconductorstructure of FIG. 14A along the vertical plane C-C′.

FIG. 15A is a top-down view of a variation of the first exemplarysemiconductor structure that can be derived from the first exemplarysemiconductor structure of FIGS. 5A-5C illustrating removal of theconductive material spikes during the fin-defining step by forming apatterned mask layer to expose portions of the base portions ofconductive material cap portions proximal to the sidewalls of the deeptrenches.

FIG. 15B is a cross-sectional view of the variation of the firstexemplary semiconductor structure of FIG. 15A along the vertical planeB-B′.

FIG. 15C is a cross-sectional view of the variation of the firstexemplary semiconductor structure of FIG. 15A along the vertical planeC-C′.

FIG. 16A is a top-down view of a second exemplary semiconductorstructure that can be derived from the first exemplary semiconductorstructure of FIGS. 10A-10C after depositing a dielectric oxide linerlayer on exposed surfaces of the semiconductor fins, the conductivestrap structures and buried insulator layer and a dielectric nitrideliner layer on the dielectric oxide liner layer according to a secondembodiment of the present application.

FIG. 16B is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 16A along the vertical plane B-B′.

FIG. 16C is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 16A along the vertical plane C-C′.

FIG. 17A is a top-down view of the second exemplary semiconductorstructure of FIGS. 16A-16C after forming dielectric caps and dielectricnitride liners in the cavities.

FIG. 17B is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 17A along the vertical plane B-B′.

FIG. 17C is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 17A along the vertical plane C-C′.

FIG. 18A is a top-down view of the second exemplary semiconductorstructure of FIGS. 17A-17C after forming gate structures, source/drainregions, outer conductive strap structures and dielectric oxide linersunderlying the dielectric nitride liners.

FIG. 18B is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 18A along the vertical plane B-B′.

FIG. 18C is a cross-sectional view of the second exemplary semiconductorstructure of FIG. 18A along the vertical plane C-C′.

FIG. 19A is a top-down view of a third exemplary semiconductor structurethat can be derived from the first exemplary semiconductor structure ofFIGS. 5A-5C or FIG. 6 after forming conductive strap structures over thedeep trench capacitors according to a third embodiment of the presentapplication.

FIG. 19B is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 19A along the vertical plane B-B′.

FIG. 19C is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 19A along the vertical plane C-C′.

FIG. 20A is a top-down view of the third exemplary semiconductorstructure of FIGS. 19A-19C after forming dielectric caps over distalportions of base portions of the conductive strap structures.

FIG. 20B is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 20A along the vertical plane B-B′.

FIG. 20C is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 20A along the vertical plane C-C′.

FIG. 21A is a top-down view of the third exemplary semiconductorstructure of FIGS. 20A-20C after forming gate structures, source/drainregions and outer conductive strap structures.

FIG. 21B is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 21A along the vertical plane B-B′.

FIG. 21C is a cross-sectional view of the third exemplary semiconductorstructure of FIG. 21A along the vertical plane C-C′.

DETAILED DESCRIPTION

The present application will now be described in greater detail byreferring to the following discussion and drawings that accompany thepresent application. It is noted that the drawings of the presentapplication are provided for illustrative purposes only and, as such,the drawings are not drawn to scale. It is also noted that like andcorresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide an understanding ofthe various embodiments of the present application. However, it will beappreciated by one of ordinary skill in the art that the variousembodiments of the present application may be practiced without thesespecific details. In other instances, well-known structures orprocessing steps have not been described in detail in order to avoidobscuring the present application.

Referring to FIGS. 1A-1C, a first exemplary semiconductor structureaccording to a first embodiment of the present application includes asemiconductor-on-insulator (SOI) substrate having deep trenches 40formed therein. The SOI substrate includes a stack of, from bottom totop, a handle substrate 10, a buried insulator layer 20, and a topsemiconductor layer 30L. In some embodiments of the present application,an optional n-doped epitaxial semiconductor layer may be present betweenthe handle substrate 10 and the buried insulator layer 20 (not shown).

The handle substrate 10 may include a semiconductor material, such as,for example, Si, Ge, SiGe, SiC, SiGeC, a compound semiconductor materialsuch as a III-V compound semiconductor material or a II-VI compoundsemiconductor material, or a combination thereof. In one embodiment, thehandle substrate 10 is composed of single crystalline silicon. Thethickness of the handle substrate 10 can be from 50 μm to 2 mm, althoughlesser and greater thicknesses can also be employed.

The buried insulator layer 20 may include a dielectric material such assilicon dioxide, silicon nitride, silicon oxynitride, or a combinationthereof. In one embodiment, the buried insulator layer 20 may be formedby a deposition process, such as chemical vapor deposition (CVD) orphysically vapor deposition (PVD). In another example, the buriedinsulator layer 20 may be formed using a thermal growth process, such asthermal oxidation, to convert a surface portion of the handle substrate10. In yet another embodiment, the buried insulator layer 20 can beformed during a SIMOX process in which oxygen ions are implanted into asemiconductor wafer and thereafter an anneal is performed to provide theSOI substrate. The thickness of the buried insulator layer 20 that isformed can be from 50 nm to 200 nm, although lesser or greaterthicknesses can also be employed.

The top semiconductor layer 30L may include a semiconductor material,such as, for example, Si, Ge, SiGe, SiC, SiGeC, a compound semiconductormaterial such as a III-V compound semiconductor material or a II-VIcompound semiconductor material, or a combination thereof. Thesemiconductor materials of the top semiconductor layer 30L and thehandle substrate 10 may be the same or different. In one embodiment, thetop semiconductor layer 30L includes a single crystalline semiconductormaterial, such as, for example, single crystalline silicon. The topsemiconductor layer 30L may be doped with p-type dopants and/or n-typedopants. Examples of p-type dopants include, but are not limited to,boron, aluminum, gallium and indium. Examples of n-type dopants, includebut are not limited to, antimony, arsenic and phosphorous. The topsemiconductor layer 30L may be formed by wafer bonding or layer transfertechniques during which a semiconductor layer is transferred from adonor wafer to a receiver wafer containing the handle substrate 10 andthe buried insulator layer 20. When a layer transfer process isemployed, an optional thinning step may follow the bonding of twosemiconductor wafers together. The optional thinning step reduces thethickness of the semiconductor layer to a layer having a thickness thatis more desirable. The top semiconductor layer 30L that is formed mayhave a thickness from 10 nm to 200 nm, although lesser or greaterthicknesses can also be employed.

At least one pad layer can be deposited on the SOI substrate (10, 20,30L), for example, by CVD or atomic layer deposition (ALD). The at leastone pad layer can include one or more layers that can be employed as anetch mask for the subsequent formation of the deep trenches 40 in theSOI substrate (10, 20, 30L). As used herein, a “deep trench” refers to atrench that extends from a topmost surface of a SOI substrate through atop semiconductor layer and a buried insulator layer and partly into anunderlying semiconductor layer. The pad layer(s) can include adielectric material and can have a thickness from 100 nm to 2 μm,although lesser and greater thicknesses can also be employed.

In one embodiment, the at least one pad layer can include a verticalstack of, from bottom to top, a pad oxide layer 42 and a pad nitridelayer 44. The pad oxide layer 42 may include a dielectric oxide materialsuch as silicon dioxide or a dielectric metal oxide. The pad nitridelayer 44 may include a dielectric nitride material such as siliconnitride or a dielectric metal nitride. In one embodiment, the thicknessof the pad oxide layer 42 can be from 2 nm to 50 nm, and the thicknessof the pad nitride layer 44 can be from 40 nm to 360 nm, although lesserand greater thicknesses can also be employed for each of the pad oxidelayer 42 and the pad nitride layer 34.

A photoresist layer (not shown) can be applied over the pad nitridelayer 44 and is lithographically patterned to form openings. Each of theopenings has an area of a deep trench 40 to be subsequently formed. Inone embodiment, the pattern for the openings can have a periodicityalong at least one horizontal direction. In one embodiment, the patternfor the openings can be periodic in two orthogonal horizontaldirections.

The pattern in the photoresist layer can be transferred into the atleast one pad layer (42, 44) to form openings in the at least one padlayer (42, 44). Subsequently, the pattern in the at least one pad layer(42, 44) can be transferred through the top semiconductor layer 30L, theburied insulator layer 20, and an upper portion of the handle substrate10 or an upper portion of the n-doped epitaxial semiconductor layer, ifpresent, by an anisotropic etch that employs the at least one pad layer(42, 44) as an etch mask. The deep trenches 40 can thus be formed in theSOI substrate (10, 20, 30L) from the pattern of openings in the at leastone pad layer (42, 44). The photoresist can be removed by ashing, or canbe consumed during the etch process that forms the deep trenches 40.

In one embodiment and as shown in FIGS. 1B and 1C, the sidewalls of thedeep trench can be substantially vertically aligned among the variouslayers (10, 20, 30L) through which the deep trench 40 extends. The depthof the deep trenches 40 as measured from the topmost surface of the SOIsubstrate (10, 20, 30L) (i.e., the top surface of the top semiconductorlayer 30L) to the bottom surface of the deep trenches 40 can be from 500nm to 10 microns, although lesser and greater depths can also beemployed. The width (i.e., the lateral distance between oppositesidewalls) of the deep trenches 40 can be from 40 nm to 150 nm, althoughlesser and greater width can also be employed. In one embodiment, thewidth of each deep trench 40 is 90 nm.

Referring to FIGS. 2A and 2B, a deep trench capacitor (12, 14, 16) isformed in a lower portion of each deep trench 40. In one embodiment, aburied plate 12 can be first formed by doping a portion of the handlesubstrate 10 in proximity of sidewalls of each deep trench 40. Dopantscan be introduced, for example, by outdiffusion from a dopant-includingdisposable material (such as a doped silicate glass) or by ionimplantation as known in the art. Further, any other method of formingburied plates 12 in the handle substrate 10 of the SOI substrate (10,20, 30L) can be employed in lieu of outdiffusion from a dopant-includingdisposable material or ion implantation.

In one embodiment and if the handle substrate 10 is doped with dopantsof a first conductivity, the buried plate 12 can be doped with dopantsof a second conductivity type which is opposite the first conductivitytype. For example, the first conductivity type can be p-type and thesecond conductivity type can be n-type, or vice versa. A p-n junction isthus formed between the remaining portion of the handle substrate 10 andeach buried plate 12. The dopant concentration in the buried plate 12can be, for example, from 1.0×10¹⁸/cm³ to 2.0×10²¹/cm³, and typicallyfrom 5.0×10¹⁸/cm³ to 5.0×10¹⁹/cm³, although lesser and greater dopantconcentrations can also be employed.

In another embodiment of the present application and when the n-dopedepitaxial semiconductor layer is present, a portion of the n-dopedsemiconductor layer surrounding each deep trench can serve as an outerelectrode for each deep trench capacitor subsequently formed andprocessing steps of forming the buried plates 12 described above can beomitted.

A node dielectric layer (not shown) can be deposited conformally onsidewalls and bottom surfaces of the deep trenches 40 as well assidewalls and the topmost surface of the at least one pad layer (42,44). The node dielectric layer can include any dielectric material thatcan be employed as a node dielectric material in a capacitor known inthe art. For example, the node dielectric layer can include at least oneof silicon nitride and a dielectric metal oxide material such as highdielectric constant (high-k) dielectric material as known in the art.

An inner electrode layer (not shown) can be deposited to completely fillthe deep trenches 40. The inner electrode layer can include a dopedsemiconductor material. The doped semiconductor material can be a dopedelemental semiconductor material, a doped compound semiconductormaterial, or an alloy thereof. In one embodiment, the inner electrodelayer includes a doped polysilicon. The inner electrode layer can bedeposited by PVD, CVD, ALD, electroplating, electroless plating, or acombination thereof. The inner electrode layer is deposited to athickness that is sufficient to completely fill the deep trenches.

In some embodiments of the present application and before filling thedeep trenches with the inner electrode layer, a metal nitride layer (notshown) may be conformally deposited over the node dielectric layer byCVD or ALD. In one embodiment, the metal nitride layer includes TiN. Themetal nitride layer is optional and can be omitted.

The inner electrode layer is vertically recessed to a level between thetop surface of the buried insulator layer 20 and the bottom surface ofthe buried insulator layer 20 by a recess etch. The recess etch of theconductive material layer can employ an anisotropic etch such as areactive ion etch (RIE), an isotropic etch such as a wet chemical etch,or a combination thereof. The recess etch can be selective to thematerial of the node dielectric layer. Each remaining portion of theinner electrode layer within the deep trenches constitutes an innerelectrode 16. The topmost surface of each inner electrode 16 issubstantially planar, and is located between the top surface of theburied insulator layer 20 and the bottom surface of the buried insulatorlayer 20.

The physically exposed portions of the node dielectric layer that arenot covered by the inner electrode 16 can be removed by a recess etch,which can be a dry etch, such as, for example, RIE. Each remainingportion of the node dielectric layer within the deep trenches 40constitutes a node dielectric 14. The topmost surface of the nodedielectric 14 is coplanar with the topmost surface of the innerelectrode 16.

Each set of a buried plate 12 around a deep trench 40, a node dielectric14, and an inner electrode 16 constitutes a trench capacitor (12, 14,16). The buried plate 12 is an outer electrode of the trench capacitor,the inner electrode 16 is the inner electrode of the trench capacitor,and the node dielectric 14 is the dielectric separating the outerelectrode (i.e., the buried plate 12) from the inner electrode 16. Thetrench capacitor (12, 14, 16) is embedded within the SOI substrate (10,20, 30L). The buried insulator layer 20 overlies, and contacts theburied plates 12. A cavity 45 is formed above the node dielectric 42 andthe inner electrode 44 within each deep trench 40.

Referring to FIGS. 3A-3C, conductive material caps 18 are formed withinthe cavities 45 and on top of the node dielectric 14 and the innerelectrode 16. The conductive material caps 18 can be formed bydepositing a conductive material in the cavities 45 and above the atleast one pad layer (42, 44), and subsequently recessing the depositedconductive material. Specifically, the conductive material can be adoped elemental semiconductor material, a doped compound semiconductormaterial, or an alloy thereof. The semiconductor material can bedeposited by CVD or PVD with in-situ doping of p-type dopants or n-typedopants. The conductive material may be deposited to a thickness that issufficient to completely fill the cavities 45.

The conductive material can be planarized, for example, by chemicalmechanical planarization (CMP) employing the pad nitride layer 44 as astopping layer. Subsequently, the conductive material is recessed to adepth at the top surface of the top semiconductor layer 30L to providethe conductive material portions 18. In one embodiment and as shown inFIGS. 3B and 3C, the top surfaces of the conductive strap structures 18are substantially coplanar with the top surface of the top semiconductorlayer 30L. A recess etch which can be an anisotropic etch such as RIEmay be employed to form the conductive material portions 18. Eachconductive material cap 18 is in contact with, and overlies, an innerelectrode 44.

Subsequently, the at least one pad layer (42, 44) is removed by at leastone etch that is selective to the semiconductor materials of the topsemiconductor layer 30L and the conductive material portions 18. Forexample, if the pad nitride layer 44 includes silicon nitride and thepad oxide layer 42 includes silicon dioxide, a wet chemical etchemploying hot phosphoric acid can be utilized to etch the pad nitridelayer 44 and a wet chemical etch employing hydrofluoric acid can beutilized to etch the pad oxide layer 42.

Referring to FIGS. 4A-4C, fin-defining mask structures 46 are formed ontop surfaces of the top semiconductor layer 30L and the conductivematerial caps 18. The fin-defining mask structures 46 are maskstructures that cover the regions of the top semiconductor layer 30Lfrom which semiconductor fins are subsequently formed. In oneembodiment, each of the fin-defining mask structures 46 can have arectangular shape and extends along a lengthwise direction. As usedherein, a “lengthwise” direction of an object refers to a directionalong which the object extends the most. The width (i.e., the lateraldistance between opposite sidewalls extending along the lengthwisedirection) of the fin-defining mask structures 46 can be from 5 nm to 30nm, although lesser and greater thicknesses can also be employed.

In one embodiment, the fin-defining mask structures 46 can be patternedportions of a dielectric hardmask layer. The fin-defining maskstructures 46 can be formed, for example, by first depositing adielectric hardmask layer (not shown) over the top semiconductor layer30L and the conductive material caps 18 and lithographically patterningthe dielectric hardmask layer. The dielectric hardmask layer includes adielectric material such as silicon dioxide, silicon nitride, adielectric metal oxide, or a combination thereof. In one embodiment, thedielectric hardmask layer includes silicon nitride. The dielectrichardmask layer can be deposited by CVD or ALD. The thickness of thedielectric hardmask layer that is formed can be from 20 nm to 200 nm,although lesser and greater thicknesses can also be employed. Thepatterning of the dielectric hardmask layer can be performed, forexample, by application and lithographic patterning of a photoresistlayer, and transfer of the patterns in the photoresist layer into thedielectric material layer by an etch, which can be an anisotropic etchsuch as RIE. Remaining portions of the photoresist layer can be removed,for example, by ashing.

In another embodiment, the fin-defining mask structures 46 can be formedby a sidewall image transfer (SIT) process. Specifically, after theformation of the dielectric hardmask layer over the top semiconductorlayer 30L and the conductive material portions 18, a mandrel materiallayer (not shown) is deposited over the dielectric hardmask layer. Themandrel material layer may be composed of amorphous silicon,polysilicon, amorphous or polycrystalline germanium, an amorphous orpolycrystalline silicon-germanium alloy material, amorphous carbon,diamond-like carbon, or organosilicate glass. The mandrel material layercan be deposited using, for example, CVD or PECVD. The thickness of themandrel material layer can be from 50 nm to 300 nm, although lesser andgreater thicknesses can also be employed. The mandrel material layerthen undergoes lithographic and etching processes to form mandrels (notshown). Next, a conformal spacer material layer (not shown) is depositedover the mandrels and exposed portions of the dielectric hardmask layerby a conformal deposition process such as, for example, CVD or ALD. Thethickness of the spacer material layer may vary depending upon thedesired width of final semiconductor fins to be formed in the topsemiconductor layer 30L, and can be from 5 nm to 30 nm, although lesserand greater thicknesses can also be employed. The spacer material layermay include a dielectric material such as silicon dioxide or siliconoxynitride. Horizontal portions of the conformal spacer material layerare then removed utilizing an anisotropic etch, such as, for example,RIE to provide spacers which are remaining portions of the spacermaterial layer on the sidewalls of the mandrels. The mandrels areremoved selective to the spacers, leaving the spacers on top of thedielectric hardmask layer. The removal of the mandrels can be performed,for example, by a wet chemical etch or a dry etch such as RIE. Thedielectric hardmask layer is subsequently patterned by an anisotropicetch using the spacers as an etch mask to provide the fin-defining maskstructures 46. The spacers are then removed by, for example, a wetchemical etch.

Referring to FIGS. 5A-5C, physically exposed portions of the topsemiconductor layer 30L and the conductive material caps 18 areanisotropically etched employing the fin-defining mask structures 46 asan etch mask to provide semiconductor layer portions 30 which areremaining portions of the top semiconductor layer 30L and conductivematerial cap portions 18A which are remaining portions of the conductivematerial caps 18. In one embodiment, the anisotropic etch can be a dryetch such as RIE that removes the semiconductor materials of the topsemiconductor layer 30L and the conductive material caps 18 selective tothe dielectric material of the buried insulator layer 20. The topsurface of the buried insulator layer 20 is thus exposed after thepatterning of the top semiconductor layer 30L and the conductivematerial caps 18.

At the end of the anisotropic etch, the exposed portions of theconductive material caps 18 may be recesses to a depth beneath the topsurface of the buried insulator layer 20, thereby forming a recessedarea 48 with a recess surface, rs₁, in the upper portion of each deeptrench 40. In one embodiment of the present application and as shown inFIG. 5C, when the anisotropic etch employed to pattern the exposedportions of the top semiconductor layer 30L and the conductive materialcaps 18 is not ideally anisotropic, such a non-ideal anisotropic etchprofile may cause portions the conductive material portions 18 along thesidewalls of the deep trenches 40 not to be completely etched away,leaving conductive material spikes 50 along the sidewalls of the upperportion of each deep trench 40. By “conductive metal spike” it is meanta vertical portion of the conductive material portions 18 that remainsalong an upper portion of the sidewall surfaces of the buried insulatorlayer 20. The conductive material spikes 50 need to be removed becausesemiconductor material epitaxially grown upon these conductive materialspikes 50 in downstream processes may short adjacent cells which leadsto the failure of deep trench capacitors (12, 14, 16). In anotherembodiment of the present application and as shown in FIG. 6, theanisotropic etch recesses the conductive material cap 18 without theformation of the conductive material spikes 50, thus producingconductive material cap portions 218A each with a planar recessedsurface.

Referring to FIGS. 7A-7C, a cut mask is applied over the fin-definingmask structures 46, the conductive material cap portions 18A and theburied insulator layer 20. The cut mask functions to remove unnecessaryfeatures formed in the previous fin-defining step which leads to theformation of the semiconductor layer portion 30. The cut mask mayinclude a material stack of, from bottom to top, an organicplanarization layer (OPL) 52L, an antireflective coating (ARC) layer 54Land a photoresist layer (not shown).

The OPL 52L may include a self-planarizing organic material which can bepolyacrylate resin, epoxy resin, phenol resin, polyamide resin,polyimide resin, unsaturated polyester resin, polyphenylenether resin,or polyphenylene sulfide resin. The OPL 52L can be applied over the overthe fin-defining mask structure 46, the conductive material cap portions18A and the buried insulator layer 20, for example, by spin-coating. TheOPL 52L that is formed thus completely fills the recessed areas 48 andhas a top surface located above the top surface of fin-defining maskstructure 46. The thickness of the OPL 52L can be from 100 nm to 400 nm,although lesser and greater thicknesses can also be employed.

The ARC layer 54L can include any antireflective material known in theart, such as, for example, a silicon-containing organic material. TheARC layer 54L can be formed, for example, by spin coating. The thicknessof the ARC layer 54L that is formed can be from 10 nm to 150 nm,although lesser and greater thicknesses can also be employed.

The photoresist layer can be a layer of a photoresist sensitive todeep-ultraviolet (DUV) radiation, extreme ultraviolet (EUV), ormid-ultraviolet (MUV) radiation as known in the art, or can be an e-beamresist that is sensitive to radiation of energetic electrons. Thephotoresist layer can be formed, for example, by spin coating. Thethickness of the photoresist layer that is formed can be from 100 nm to600 nm, although lesser and greater thicknesses can also be employed.

The photoresist layer is lithographically patterned to form a pattern ofopenings therein. The openings overlie unwanted dummy fins to be cut(i.e., removed). The remaining portions of the photoresist layer areherein referred to as photoresist layer portions 56. A portion of eachphotoresist layer portion 56 can overlie a portion of a semiconductorlayer portion 30 and a portion of a conductive material cap portion 18Awhich laterally contacts the portion of the semiconductor layer portion30. In one embodiment, a photoresist layer portion 56 can overlie a pairof conductive material cap portions 18A.

Referring to FIGS. 8A-8C, the pattern of openings in the photoresistlayer is transferred into the SiARC layer 54L and the OPL 52L by atleast one anisotropic etch. In one embodiment, the SiARC layer 54L maybe etched by a dry etch employing a fluorocarbon-containing plasma, andthe OPL 52L may be etched employing an oxygen-containing plasma. Thephotoresist layer portions 56 acts as an etch mask for the etch of theSiARC layer 54L, and may be removed during the etch of the OPL 52L or bythe end of OPL 52L patterning. The OPL 52L etch could be a full OPL etchor partial OPL etch as long as at least portions of the fin-definingmask structures 46 are exposed. The remaining portions of the SiARClayer 54L are herein referred to the SiARC layer portions 54. Theremaining portions of the OPL 52L are herein referred to the OPLportions 52.

Referring to FIGS. 9A-9C, portions of the fin-defining mask structures46 and the underlying unwanted portions of the semiconductor layerportions 30 and portions of the conductive material cap portions 18Athat adjoin the unwanted portions of the semiconductor layer portions 30that are not covered by the SiARC layer portions 54 and the OPL portions52 are removed. An anisotropic etch, which can be a dry etch or a wetchemical etch, may be performed to remove the materials of thefin-defining mask structures 46, the semiconductor layer portions 30 andthe conductive material cap portions 18A selective to materials of theburied insulator layer 20. The SiARC layer portions 54 may also beremoved during the removal of the exposed portions of the semiconductorfins 30F and conductive material cap portions 18A. The remainingportions of the semiconductor layer portions 30 are herein referred toas semiconductor fins 30F. The remaining portions of conductive materialcap portions 18A are herein referred to as patterned conductive materialcap portions 18P. Each patterned conductive material cap portion 18Pincludes a fin portion 18F laterally contacting a semiconductor fin 30Fand a sidewall of the buried insulator layer 20 and a base portion 18Bthat underlies the fin portion 18F vertically contacting the innerelectrode 16.

The anisotropic etch may be continued to remove portions of the OPLportions 52 from the recessed areas 48 to expose portions of the baseportions 18B of the patterned conductive material cap portions 18Pproximal to the sidewalls of the deep trenches 40. The conductivematerial spikes 50 are thus exposed. The semiconductor fins 18F and thefin portions 18F of the patterned conductive material cap portions 18Premain covered by the OPL portions 52.

Referring to FIGS. 10A-10C, the conductive material spikes 50 areremoved from the sidewalls of the deep trenches 40 by an isotropic etch.The isotropic etch may be a wet chemical etch wet or a dry etch thatremoves the conductive material spikes 50 selective to OPL 52 and theburied insulator 20. In one embodiment, a fluorine containing plasma canbe employed for the removal of the conductive material spikes 50. Aspike-free deep trench sidewall surface is thus provided at an upperportion of each deep trench 40. The portions of the base portions 18B ofthe patterned conductive material cap portions 18P proximal to thesidewalls of the deep trenches 40 are also recessed by the isotropicetch, while the fin portions 18F of the patterned conductive materialcap portions 18P that are covered by the OPL portions 52 remain intactalthough etching of the OPL portions 52 may occur during the isotropicetch. The remaining portion of each patterned conductive material capportion 18P is herein referred to as a conductive strap structure 18C.This step provides a second recessed surface, rs₂, within the baseportion of each conductive strap structure 18C which is deeper than therecessed surface, rs₁, thus forming conductive strap structure 18Chaving a stepped base portion 18B′ and a fin portion 18F′ extending fromthe stepped base portion 18B′. The fin portion 18F′ laterally contacts asemiconductor fin 30F. In the stepped base portion 18B′, a sidewallsurface of the conductive strap structure 18C extends from the firstrecessed surface rs₁ to the second recessed surface rs₂. In anotherembodiment and when the conductive material spikes 50 are removed or arenot present from prior patterning, the second recessed surface rs₂ wouldbe at the same level as the recessed surface rs₁.

Upon formation of the conductive strap structures 18C, remainingportions of the OPL portions 52 are removed. In one embodiment, theremaining OPL portions 52 may be removed by, for example, plasmastripping or a wet chemical etch. A cavity 58 is thus is formed abovethe conductive strap structure 18C within each deep trenches 40.

In the present application and because the semiconductor fins 30F remainprotected by the OPL portions 52 during the removal of the conductivematerial spikes 50 from the sidewalls of the deep trenches 40, theprofile and dimensions of semiconductor fins 30F are preserved. Inaddition, because no separate mask is needed in the removal of theconductive material spikes 50, the approach of the present applicationallows reducing the number of masks and simplification of themanufacturing processes, thereby saving material and cost.

Referring to FIGS. 11A-11C, a dielectric cap layer 60L is deposited inthe cavities 58 and over the buried insulator layer 20 and thefin-defining mask structures 46. The dielectric cap layer 60L mayinclude a dielectric oxide such as silicon dioxide, or a rare earthoxide. The dielectric cap layer 60L can be deposited, for example, byCVD or PECVD to a thickness to completely fill the cavities 58 withinthe deep trenches 40. A top surface of the dielectric cap layer 60L islocated above the top surface of the fin-defining mask structures 46. Insome embodiments of the present application, prior to the deposition ofthe dielectric cap layer 60L, a bilayer liner including a layer ofsilicon dioxide and an overlying layer of silicon nitride may bedeposited on exposed surfaces of the cavities 58 to protect thesemiconductor fins 30F.

Referring to FIGS. 12A-12C, dielectric caps 60 are formed in thecavities 58. The dielectric cap layer 60L is first recessed by an etchback process till the top surfaces of the fin-defining mask structures46 are exposed. The etch back process can be CMP, RIE or a combinationthereof. The fin-defining mask structures 46 may be partially removed bythe etch back process employed to recess the dielectric cap layer 60L

Subsequently, the fin-defining mask structures 46 are completely removedfrom the top of semiconductor fins 30F by an etch, which can be a wetchemical etch or a dry etch. In one embodiment and when each of buriedinsulator layer 20 and the dielectric cap layer 60L is composed ofsilicon dioxide and the fin-defining mask structures 46 are composed ofsilicon nitride, a wet chemical etch employing hot phosphoric acid canbe employed to remove the fin-defining mask structures 46 from the topof the semiconductor fins 30F. After the removal of the fin-definingmask structures 46, the dielectric cap layer 60L is further recessed toprovide the dielectric cap 60. The topmost surface of each dielectriccap 60 is coplanar with the top surface of the buried insulator layer20.

Each dielectric cap 60 thus formed vertically contacts a stepped baseportion 18B′ and laterally surrounding a portion of the fin portion 18F′of a conductive strap structure 18C. The entirety of sidewalls of thedielectric cap 60 is vertically coincident with the entirety ofsidewalls of the conductive strap structure 18C.

Referring to FIGS. 13A-13C, gate structures are formed overlyingportions of the semiconductor fins 30F. Each gate structure includes agate stack straddling over a portion of a semiconductor fin 30F and agate spacer 68 formed on each sidewall of the gate stack. In oneembodiment and as shown in FIG. 13A, two gate stacks can straddle twoparallel portions of one semiconductor fin 30F. The gate stack includes,from bottom to top, a gate dielectric 62, a gate electrode 64 and a gatecap 66. The gate stacks (62, 64, 66) may be formed by first providing agate material stack (not shown) that includes, from bottom to top, agate dielectric layer, a gate electrode layer and a gate cap layer overthe semiconductor fins 30F, the conductive strap structures 18C, thedielectric caps 60 and the buried insulator layer 20.

The gate dielectric layer can be formed by converting surface portionsof the semiconductor fins 30F into a dielectric semiconductor-containingmaterial such as a dielectric semiconductor oxide, a dielectricsemiconductor nitride, a dielectric semiconductor oxynitride, or acombination thereof. For example, if the semiconductor fins 30F includesilicon, the dielectric semiconductor-containing material can be silicondioxide, silicon nitride, silicon oxynitride, or a combination thereof.The thickness of the gate dielectric layer can be, for example, from 0.5nm to 6 nm, although lesser and greater thicknesses can also beemployed. Alternately or additionally, the gate dielectric layer can beformed by depositing a dielectric material. In one embodiment, thematerial of the gate dielectric layer can be deposited by a conformaldeposition method such as ALD or CVD. In one embodiment, the depositeddielectric material can include a dielectric semiconductor oxide such assilicon dioxide. In another embodiment, the deposited dielectricmaterial can include a dielectric metal oxide, a dielectric metalnitride, and/or a dielectric metal oxynitride. In one embodiment, thedeposited dielectric material can include a high-dielectric constant(high-k) gate dielectric material known in the art. Exemplary high-kmaterials include, but are not limited to, HfO₂, ZrO₂, La₂O₃, Al₂O₃,TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, HfO_(x)N_(y), ZrO_(x)N_(y), La₂O_(x)N_(y),Al₂O_(x)N_(y), TiO_(x)N_(y), SrTiO_(x)N_(y), LaAlO_(x)N_(y),Y₂O_(x)N_(y), SiON, SiN_(x), a silicate thereof, and an alloy thereof.Each value of x is independently from 0.5 to 3 and each value of y isindependently from 0 to 2.

The gate electrode layer includes a conductive material, which caninclude a doped semiconductor material such as doped polysilicon, ametallic material such as Al, Au, Ag, Cu or W, or combinations thereof.The gate electrode layer can be deposited, for example, by CVD, PVD, orany other known method for depositing a conductive material. Thethickness of the gate electrode layer, as measured in planar regions,can be from 20 nm to 300 nm, although lesser and greater thicknesses canalso be employed.

The gate cap layer includes a dielectric material such as siliconnitride, silicon dioxide, silicon oxynitride, and/or a dielectric metaloxide. The gate cap layer can be deposited, for example, by CVD. Thethickness of the gate cap layer can be from 5 nm to 50 nm, althoughlesser and greater thicknesses can also be employed.

The gate material stack can then be patterned by lithography and etchingto form the gate stacks (62. 64, 66). Specifically, a photoresist layer(not shown) is applied over the topmost surface of the gate materialstack and is lithographically patterned by lithographic exposure anddevelopment. The pattern in the photoresist layer is transferred intothe material stack by an etch, which can be an anisotropic etch such asRIE. The remaining portions of the material stack after the patterntransfer constitute the sacrificial gate stack (62, 64, 66). Thepatterned photoresist layer may be subsequently removed by, for example,ashing.

The gate spacer 68 may include a dielectric material such as, forexample, an oxide, a nitride, an oxynitride, or any combination thereof.For example, the gate spacer 68 may be composed of silicon nitride,silicon boron carbon nitride, or silicon carbon oxynitride. The gatespacer 68 can be formed by first providing a conformal gate spacermaterial layer (not shown) on exposed surfaces of the gate stacks (62,64, 66), the semiconductor fins 30F, the conductive strap structures18C, the dielectric caps 60 and the buried insulator layer 20 and thenetching the conformal gate spacer material layer to remove horizontalportions of the conformal gate spacer material layer. The conformal gatespacer material layer can be provided by a deposition process including,for example, CVD, PECVD, or PVD. The etching of the conformal gatespacer material layer may be performed by a dry etch process such as,for example, RIE. The remaining portions of the conformal gate spacermaterial layer constitute the gate spacer(s) 68. The width of each gatespacer 68, as measured at the base of the gate spacer 68 can be from 5nm to 100 nm, although lesser and greater widths can also be employed.

In some embodiments of the present application, the gate stacks (62, 64,66) are sacrificial gate stacks for a replacement gate process and canbe replaced with functional gate stacks after the formation of thesource/drain regions employing methods known in the art. The term“sacrificial gate stack” as used herein denotes a structure that servesas a placeholder for a functional gate stack to be subsequently formed.The term “functional gate stack” as used herein denotes a permanent gatestack used to control output current (i.e., flow of carriers in thechannel) of a semiconducting device through electrical fields.

Referring to FIGS. 14A-14C, a semiconductor material is selectivelydeposited on exposed surfaces of the semiconductor fins 30F and theconductive strap structures 18C to form a raised source region and araised drain region (collectively referred to as raised source/drainregions 72) on portions of the semiconductor fins 30F located onopposite sides of each gate structure (62, 64, 66, 68) and an outerconductive strap structure 76 on each conductive strap structure 18C. Inone embodiment and as shown in FIG. 13A, source/drain regions 72 betweenadjacent gate structures (62, 64, 66, 68) may be merged. Each outerconductive strap structure 76 contacts sidewalls and a top surface of afin portion 18F′ of a conductive strap structure 18C.

The semiconductor material of the raised source/drain regions 72 and theouter conductive strap structures 76 can be selected from, but are notlimited to, silicon, silicon germanium, silicon carbon, silicongermanium carbon, a compound semiconductor material, or an alloythereof. The deposition of the semiconductor material can be performed,for example, by a selective epitaxy process. During the selectivedeposition of the semiconductor material, the semiconductor material isdeposited on semiconductor surfaces of the semiconductor fins 30F andthe conductive strap structures 18C, but not on dielectric surfaces suchas the surfaces of the gate caps 66, the gate spacers 68, the dielectriccaps 60 and the buried insulator layer 20. In one embodiment, the raisedsource/drain regions 72 can be formed as a single crystallinesemiconductor material portion that is in epitaxial alignment with asingle crystalline semiconductor material of the semiconductor fins 30F.By “epitaxial alignment” it is meant that the raised source/drainregions 72 have a same crystal orientation as that of the underlyingsemiconductor fins 30F. The outer conductive strap structures 76 can beformed as polycrystalline semiconductor material portions. Thethicknesses of the raised source/drain regions 72 and the outerconductive strap structures 76, as measured above a top surface of asemiconductor fin 30F or above a topmost surface of a contact strapstructure 18C, can be from 1 nm to 50 nm, although lesser and greaterthicknesses can also be employed. With the removal of the conductivespike 50, and covering the top of the trenches with dielectric caps 60,the deep trench shorting mechanisms through the raised source drainregion 72 is eliminated.

The raised source/drain regions 72 and the outer conductive strapstructures 76 are doped with n-type or p-type dopants. For nFinFETs, thesource/drain regions 72 are doped n-type, while for pFinFETs, thesource/drain regions 72 are doped p-type. The doping of the source/drainregions 72 and the outer conductive strap structures 76 can be formedin-situ during the epitaxial growth of the semiconductor material.Alternatively, the doping of the source/drain regions 72 and the outerconductive strap structures 76 can be formed after the epitaxial growthof the semiconductor material by ion implantation, gas phase doping orout diffusion of a dopant from a sacrificial material layer include saiddoping. Dopants in the source/drain regions 72 and the outer conductivestrap structures 76 can be subsequently activated, for example, by laseranneal.

In the present application and because the epitaxial growth of thesemiconductor material during the formation of source/drain regions 72of FinFETs does not occur on dielectric surfaces of the dielectric cap60, the presence of the dielectric cap 60 over the top of the baseportion 18B′ of the conductive strap structure 18C prevents theepitaxially grown semiconductor material in adjacent deep trenches 40from touching each other, thus preventing the electrical shorts betweenthe adjacent deep trench capacitors (12, 14, 16). In addition and in thecase where the dielectric cap 60 is eroded at portion proximal to thesidewalls of the deep trench 40, the stepped structure of the baseportion of the conductive strap structure 18C resulting from the removalof the conductive material spikes 50 from the sidewalls of the deeptrench 40 makes the stepped base portion 18B′ of the conductive strapstructure 18C less likely to be exposed, thus further reducing thepossibility and almost eliminating the electrical shorts betweenadjacent deep trench capacitors (12, 14, 16).

Referring to FIGS. 15A-15C, a variation of the first exemplarysemiconductor structure can be derived from the first exemplarysemiconductor structure of FIGS. 5A-5C by removing the conductivematerial spikes 50 during the fin-defining step rather than the dummyfin cutting step. After the formation of the semiconductor layerportions 30 and the conductive material cap portions 18A, a mask layer80 is applied over the fin-defining mask structures 46 and the buriedinsulator layer 20 and lithographically patterned to expose portions ofbase portions of conductive material cap portions 18A proximal to thesidewalls of the deep trenches 40. The conductive material spikes 50 arethus exposed. The mask layer 80 can be a photoresist layer or aphotoresist layer in conjunction with hardmask layer(s).

The isotropic etch of FIGS. 10A-10C is performed to remove theconductive material spikes 50 from the sidewalls of the deep trenches40. The remaining portions of the mask layer 80 that protect thesemiconductor layer portions 30 during the isotropic etch can besubsequently removed by, for example, ashing. A patterned conductivematerial cap portion 118P is thus formed over the deep trench capacitor(14, 16, 18) in each deep trench 40. Each patterned conductive materialcap portion 118P contains a stepped base portion 118B and a fin portion118F extending from the stepped base portion 118B. The stepped baseportion 118B has a first recessed surface rs₁ located below the topsurface of the buried insulator layer 20 by a first depth and a secondrecessed surface rs₂ located below the top surface of the buriedinsulator layer 20 by a second depth which is greater than the firstdepth.

The processing steps of FIGS. 7A-7C, 8A-8C and 9A-9C are subsequentlyperformed to remove portions of the unwanted semiconductor layerportions 30 and portions of the patterned conductive cap portions 118adjoined to the unwanted semiconductor layer portions 30 to provide thesemiconductor fins 30F and the conductive strap structures 18C.

Referring to FIGS. 16A-16C, a second exemplary semiconductor structureaccording to a second embodiment of the present application can bederived from the first exemplary semiconductor structure of FIGS.10A-10C by depositing a dielectric oxide liner layer 82L on exposedsurfaces of the semiconductor fins 30F, the conductive strap structures18C and buried insulator layer 20 and a dielectric nitride liner layer84L on the dielectric oxide liner layer 82L. The dielectric oxide linerlayer 82L may include a silicon dioxide. The dielectric oxide linerlayer 82L can be formed, for example, by CVD or PECVD. The dielectricoxide liner layer 82L that is formed can have a thickness from 5 nm to10 nm, although lesser and greater thicknesses can also be employed. Thedielectric nitride liner layer 84L may include silicon nitride. Thedielectric nitride liner layer 84L can be formed, for example, by CVD orPECVD. The dielectric nitride liner layer 84L that is formed can have athickness from 5 nm to 10 nm, although lesser and greater thicknessescan also be employed.

Referring to FIGS. 17A-17C, the processing steps of FIGS. 11A-11C areperformed to form a dielectric cap layer over the dielectric nitrideliner layer 84L. The processing steps of FIGS. 12A-12C are performed toform dielectric caps 60 within the remaining volumes of the cavities 58.Subsequently, portions of the dielectric nitride liner layer 84L thatare not covered by the dielectric caps 60 are removed by at least oneetch which can be a dry etch or a wet chemical etch. Remaining portionsof the dielectric nitride liner layer 84L within the deep trenches 40constitute the dielectric nitride liners 84.

Referring to FIGS. 18A-18C, processing steps of FIGS. 13A-13C areperformed to provide gate structures (62, 64, 66, 68) each of whichoverlying a channel portion of a semiconductor fin 30F. During thelithographic patterning of the gate material stack, portions of thedielectric oxide layer 82L that are not covered by the patternedphotoresist layer are also removed from exposed surfaces of thesemiconductor fins 30 and the fin portions of the conductive strapstructures 18C, and the top surface of the buried insulator layer 20.Each of the gate structures thus formed includes a gate stack including,for bottom to top, an interfacial dielectric oxide 82A which areremaining sub-portions of the dielectric oxide liner layer 82 underlyingthe patterned gate material stack, a gate dielectric 62, a gateelectrode 64 and a gate cap 66, and a gate spacer 68 present on eachsidewall of the gate stack (82A, 62, 64, 66). Remaining sub-portions ofthe dielectric oxide liner layer 82L located within the deep trenches 40are herein referred to as the dielectric oxide liners 82B.

Subsequently, processing steps of FIGS. 14A-14C may be performed to formsource/drain regions 72 on portions of the semiconductor fins 30F onopposite side of the gate structures (82A, 62, 64, 66, 68) and outerconductive strap structures 74 on exposed surfaces of the conductivestrap structures 18C.

Referring to FIGS. 19A-19C, a third exemplary semiconductor structureaccording to a third embodiment of the present application can bederived from the first exemplary semiconductor structure of FIGS. 5A-5Cor FIG. 6 after removing unwanted portions of the semiconductor layerportions 30 (i.e., dummy fins) by performing processing steps of FIGS.7A-7C, 8A-8B and 9A-9C to produce a conductive strap structure 218C witha fin portion 218F′ and a base portion 218B′ on top of each deep trenchcapacitor (12, 14, 16). The removal of the conductive spikes 50 can beomitted when the conductive material spikes 50 are present deep enoughin the deep trenches 40 such that erosion of the dielectric cap laterformed would never expose the conductive spikes 50. During the dummy fincut process, a distal portion of a base portion of each conducivematerial cap portion 18A/218A (i.e., a portion of the base portion ofthe conductive material cap portion 18A/218A that is located away fromthe adjoined semiconductor layer portion 30) is recessed to a greaterdepth than that of a proximal portion of the conductive material portion18A (i.e., a portion of the base portion over which the fin portion ofthe conducive material cap portion 18A/218A extends) because theproximal portion of the conductive material portion 18A/218A is coveredby the fin cut mask. The base portion 218B′ of each conductive strapstructure 218C thus has a distal portion with a top surface verticallyoffset form a top surface of a proximal portion. The recessing of theconductive material cap portions 18A/218A forms a cavity 258 above thebase portion 218B′ of each conductive strap structure 218C in the deeptrench 40.

Referring to FIGS. 20A-20C, a dielectric cap layer (not shown) isdeposited in the cavities 258 and over the buried insulator layer 20 andthe fin-defining mask structures 46 by the processing steps of FIGS.11A-11C. The dielectric cap layer is then recessed vertically by ananisotropic etch that removes the dielectric material of the dielectriccap layer 40 selective to the semiconductor materials of thesemiconductor fins 30F and the conductive strap structures 218C. In oneembodiment, the dielectric cap layer is recessed to a depth such thatportions of the dielectric cap layer that are present on the proximalportions of the base portions 218B′ of the conductive strap structures218C is completely removed. Remaining portions of the dielectric caplayer that are present on the distal portions of the base portions 218B′of the conductive strap structures 218C constitutes the dielectric caps260. The etch chemistry employed to recess the dielectric cap layer alsorecesses exposed portions of the buried insulator layer 20 that are notcovered by the semiconductor fins 30F, thus forming a dielectric fin 20Funder each semiconductor fin. Each dielectric fin 20F and acorresponding overlying semiconductor fin 30F together constitutes a finstack. The top surfaces of the proximal portions of the conductive strapstructures 218C are coplanar with the recessed surface of the buriedinsulator layer 20.

Referring to FIGS. 20A-20C, processing steps of FIGS. 13A-13C areperformed to provide gate structures each of which straddling over aportion of a vertical stack of a semiconductor fin 30F and a dielectricfin 20. Each of the gate structures thus formed includes a gate stackincluding, for bottom to top, a gate dielectric 62, a gate electrode 64and a gate cap 66, and a gate spacer 68 present on each sidewall of thegate stack (62, 64, 66). Remaining sub-portions of the dielectric oxideliner layer 82L located within the deep trenches 40 are herein referredto as the dielectric oxide liners 82B.

Subsequently, processing steps of FIGS. 14A-14C may be performed to formsource/drain regions 72 on portions of the semiconductor fins 30F onopposite side of the gate structures (82A, 62, 64, 66, 68) and outerconductive strap structures 274 on exposed surfaces of the conductivestrap structures 18C. Due to the presence of the dielectric caps 260 onthe distal portions of the base portions 218B′ of the conductive strapstructures 218C, the semiconductor material can only be epitaxiallydeposited on the proximal portions of the base portions 218B′ of theconductive strap structures 218C, but not on the distal portions of thebase portions 218B′ of the conductive strap structures 218C. As aresult, the electrical shorts between adjacent deep trench capacitorscan be prevented.

While the application has been described in terms of specificembodiments, it is evident in view of the foregoing description thatnumerous alternatives, modifications and variations will be apparent tothose skilled in the art. Each of the embodiments described herein canbe implemented individually or in combination with any other embodimentunless expressly stated otherwise or clearly incompatible. Accordingly,the application is intended to encompass all such alternatives,modifications and variations which fall within the scope and spirit ofthe application and the following claims.

What is claimed is:
 1. A method of forming a semiconductor structurecomprising: forming a deep trench extending through a top semiconductorlayer, a buried insulator layer and into a handle substrate of asemiconductor-on-insulator (SOI) substrate; forming a deep trenchcapacitor in a lower portion of the deep trench; forming a conductivematerial cap over the deep trench capacitor to completely fill the deeptrench; forming a laterally contacting pair of a semiconductor fin and aconductive strap structure by patterning the top semiconductor layer andthe conductive material cap, wherein the conductive strap structurecomprises a stepped base portion vertically contacting the deep trenchcapacitor and a fin portion extending from the base portion andlaterally contacting the semiconductor fin; and forming a dielectric capover the stepped base portion of the conductive strap structure to fillthe deep trench.
 2. The method of claim 1, wherein the stepped baseportion comprises a first recessed surface located below a top surfaceof the buried insulator layer by a first depth and a second recessedsurface located below the top surface of the buried insulator layer by asecond depth greater than the first depth.
 3. The method of claim 2,wherein forming the laterally contacting pair of the semiconductor finand the conductive strap structure comprises: forming a fin-definingmask structure over the top semiconductor layer and the conductivematerial cap; patterning the top semiconductor layer and the conductivematerial cap by employing the fin-defining mask structure as an etchmask to provide a top semiconductor layer portion and a conductivematerial cap portion; removing an unwanted portion of the topsemiconductor layer portion and a portion of the conductive material capportion adjoined to the unwanted portion of the top semiconductor layerportion to provide a laterally contacting pair of the semiconductor finand a patterned conductive material cap portion, wherein the patternedconductive material cap portion has a fin portion laterally contactingthe semiconductor fin and a base portion having the first recessedsurface, wherein the laterally contacting pair of the semiconductor finand the patterned conductive material cap portion is covered by a cutmask portion; removing a portion of cut mask portion to expose portionsof the base portion of the patterned conductive material cap portionproximal to sidewalls of the deep trench; and removing conductivematerial spikes in the exposed portions of the base portion of thepatterned conductive material cap portion from the sidewalls of the deeptrench by an isotropic etch to provide the conductive strap structure,wherein the isotropic etch recesses the exposed portions of the baseportion of the patterned conductive material cap portion to provide thesecond recessed surface.
 4. The method of claim 3, wherein the formingthe dielectric cap comprises: depositing a dielectric cap layer over theconductive strap structure, the fin-defining mask structure and theburied insulator layer, the dielectric cap layer having a top surfaceabove a top surface of the fin-defining mask structure; recessing thedielectric cap layer to provide the dielectric cap, the dielectric caphaving a top surface coplanar with a top surface of the buried insulatorlayer; and removing the fin-defining mask structure.
 5. The method ofclaim 4, further comprising: forming a dielectric oxide liner layer overthe conductive strap structure, the fin-defining mask structure and theburied insulator layer; and forming a dielectric nitride liner layerover the dielectric oxide liner layer prior to the forming thedielectric cap layer.
 6. The method of claim 5, further comprisingremoving portions of the dielectric nitride liner layer and thedielectric oxide liner layer that are not covered by the dielectric capafter the forming the dielectric cap.
 7. The method of claim 2, whereinforming the laterally contacting pair of the semiconductor fin and theconductive strap structure comprises: forming a fin-defining maskstructure over the top semiconductor layer and the conductive materialcap; patterning the top semiconductor layer and the conductive materialcap by employing the fin-defining mask structure as an etch mask toprovide a top semiconductor layer portion and a conductive material capportion, wherein the conductive material cap portion has a fin portionlaterally contacting the top semiconductor layer portion and a baseportion having the first recessed surface; forming a patterned masklayer to cover a portion of the conductive material cap portion and toexpose portions of the base portion proximal to sidewalls of the deeptrench; removing conductive material spikes in the exposed portion ofthe base portion of the conductive material cap portion from thesidewalls of the deep trench by an isotropic etch, wherein the isotropicetch recesses the exposed portions of the base portion of the conductivematerial cap portion to the second depth; removing the patterned masklayer; and removing an unwanted portion of the top semiconductor layerportion and a portion of a remaining portion of the conductive materialcap portion adjoined to the unwanted portion of the top semiconductorlayer portion.
 8. The method of claim 1, wherein the dielectric caplaterally surrounds a lower portion of the fin portion of the conductivestrap structure.
 9. The method of claim 1, further comprising forming agate structure straddling a portion of the semiconductor fin, whereinthe gate structure comprises a gate stack and a gate spacer present onsidewalls of the gate stack.
 10. The method of claim 9, wherein theforming the gate stack comprises: forming a gate material stackcomprising, from bottom to top, a gate dielectric layer, a gateelectrode layer and a gate cap layer over the semiconductor fin, theconductive strap structure, the dielectric cap and the buried insulatorlayer; and patterning the gate material stack to provide the gate stack.11. The method of claim 9, further comprising forming raisedsource/drain regions on portions of the semiconductor fin located onopposite sides of the gate structure and forming an outer conductivestrap structure on the conductive strap structure.
 12. The method ofclaim 11, wherein the forming raised source/drain regions and theforming outer conductive strap structure comprises epitaxiallydepositing a semiconductor material on physically exposed surfaces ofthe portions of the semiconductor fin that are not covered by the gatestructure and on physically exposed surfaces of a portion of the finportion of the conductive strap structure that is not located above thedielectric cap.
 13. A method of forming a semiconductor structurecomprising: forming a deep trench extending through a top semiconductorlayer, a buried insulator layer and into a handle substrate of asemiconductor-on-insulator (SOI) substrate; forming a deep trenchcapacitor in a lower portion of the deep trench; forming a conductivematerial cap over the deep trench capacitor to completely fill the deeptrench; forming a laterally contacting pair of a semiconductor fin and aconductive strap structure by patterning the top semiconductor layer andthe conductive material cap, wherein the conductive strap structurecomprises a base portion vertically contacting the deep trench capacitorand a fin portion extending from a proximal portion of the base portionand adjoined to the semiconductor fin; forming a dielectric cap layerover the laterally contacting pair of the semiconductor fin and theconductive strap structure and the buried insulator layer; and recessingthe dielectric cap layer and the buried insulator layer, wherein therecessing the dielectric cap layer provides a dielectric cap over adistal portion of the base portion of the conductive strap structureadjoined to the proximal portion, and the recessing the buried insulatorlayer provides a dielectric fin beneath the semiconductor fin.
 14. Themethod of claim 13, wherein the recessing the dielectric cap layercompletely removes a portion of the dielectric cap layer present on theproximal portion of the base portion of the conductive strap structureand removes a portion of the buried insulator layer, wherein a topsurface of the distal portion of the base portion is coplanar with a topsurface of a recessed portion of the buried insulator layer.
 15. Themethod of claim 13, wherein the forming the laterally contacting pair ofthe semiconductor fin and the conductive strap structure comprises:forming a fin-defining mask structure over the top semiconductor layerand the conductive material cap; removing portions of the topsemiconductor layer and the conductive material cap that are not coveredby the fin-defining mask structure; and removing a portion of aremaining portion of the top semiconductor layer and a portion of aremaining portion of the conductive material cap adjoined the portion ofthe remaining portion of the top semiconductor layer.
 16. The method ofclaim 15, further comprising removing the fin-defining mask structurefrom top surfaces of the semiconductor fin and the fin portion of theconductive strap structure.
 17. The method of claim 13, wherein a topsurface of the distal portion of the base portion is located below a topsurface of the proximal portion of the base portion.
 18. The method ofclaim 13, further comprising forming a gate structure straddling aportion of the semiconductor fin, wherein the gate structure comprises agate stack and a gate spacer present on sidewalls of the gate stack. 19.The method of claim 18, wherein the forming the gate stack comprises:forming a gate material stack comprising, from bottom to top, a gatedielectric layer, a gate electrode layer and a gate cap layer over thesemiconductor fin, the conductive strap structure, the dielectric capand the buried insulator layer; and patterning the gate material stackto provide the gate stack.
 20. The method of claim 9, further comprisingforming raised source/drain regions on portions of the semiconductor finlocated on opposite sides of the gate structure and forming an outerconductive strap structure on the conductive strap structure.